Integration of chip level micro-fluidic cooling in chip packages for heat flux removal

ABSTRACT

An electronic chip package includes a base defining a fluid inlet opening for receiving pressurized fluid from a fluid source and a fluid outlet opening. A dielectric body is arranged on the base and configured to support an electronic device. The dielectric body comprises a coolant flow chamber formed in a first surface thereof, and a plurality of impingement openings formed within the coolant flow chamber. The plurality of impingement openings are in communication with the fluid inlet opening of the base for generating a plurality of fluid streams to be expelled into the coolant flow chamber. The body further comprises a coolant return port formed within the coolant flow chamber and in communication with the fluid outlet opening of the base.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and is a divisional application of co-pending U.S. patent application Ser. No. 15/599,781, entitled INTEGRATION OF CHIP LEVEL MICRO-FLUIDIC COOLING IN CHIP PACKAGES FOR HEAT FLUX REMOVAL, filed May 19, 2017, which is a divisional of issued U.S. Pat. No. 9,659,838 filed on Mar. 28, 2016 and issued on May 23, 2017, the entire contents of which are herein incorporated by reference for all purposes.

FIELD OF THE INVENTION

The present disclosure relates to cooling systems and methods for use with electronic circuits, and more particularly, to integrated circuit packages featuring embedded cooling provisions.

BACKGROUND

The performance of many commercial and military electronic systems, including digital, power and microwave systems, is constrained by the cooling capabilities of conventional thermal management systems and methods. Heat flux within devices continues to increase as new technologies are developed. For example, enhanced performance capabilities of digital processors and associated memory devices are accompanied by increased heat generation. Likewise, power devices such as amplifiers, regulators and power converters continue to provide increased capability despite smaller packaging, resulting in higher dissipated power densities.

In the microwave field, the introduction of Gallium Nitride (GaN) transistors in place of traditional gallium arsenide (GaAs) devices has resulted in heat flux increases of at least one order of magnitude. For example, field effect transistors (FETs) produced in GaN can dissipate about 10 watts per millimeter (W/mm) of gate width compared to 1 W/mm in GaAs FETs. Microwave amplifiers, often embodied as monolithic microwave integrated circuits (MMICs), are built by grouping these FETs side by side and in multiple stages to realize a desired or target gain and RF power of a given device. The resulting power density in these MMIC amplifiers has increased from approximately 100 watts per square centimeter (W/cm²) in GaAs applications, to approximately 30K W/cm² in GaN configurations. In addition, GaN devices can withstand higher temperatures compared to GaAs devices, and thus are operated at higher drive levels which leads to even higher power densities. These high power GaN microwave amplifiers are used in applications ranging from cellular systems (e.g. cellular phones) to radars, target illuminators, communication devices and electronic warfare equipment for the defense industry. The performance of these devices has become limited by the abilities of conventional cooling techniques to efficiently remove the increased heat generated by these systems.

Referring generally to FIG. 1, there is shown a typical “remote cooling” thermal management system 10 for use with small-scale electronics, including integrated circuit packages. Heat generated by a source, embodied herein as a circuit die 12, is transferred through multiple intermediate material layers arranged between die 12 and a heat sink, such as a liquid-cooled cold plate 19. These layers may include, for example, a solder layer 13, a heat sink or heat spreading layer 14, a first epoxy layer 15, a module package including ceramic layer 16 (e.g. a transmitter/receiver module package), and a second epoxy layer 17 for attaching the module package to cold plate 19. As illustrated, each material presents a thermal resistance (Rth) to heat flow and adds to the overall thermal rise from the coolant to the device junction. While such assemblies provide some level of effectiveness, increases in device power and density resulting from packaging multiple devices together, have created systems with even greater cooling requirements. These systems, in many cases, exceed the capability of the present remote cooling approaches to maintain acceptable junction temperatures.

Alternate thermal management systems and techniques are needed.

SUMMARY

In one embodiment of the present disclosure, a substrate body for supporting an electronic device is provided. The body includes at least one electrical circuit formed thereon configured to be connected to the electronic device. A plurality of impingement openings are formed through the body, with each impingement opening configured to be responsive to a source of pressurized fluid for generating a fluid stream to be expelled in a direction of the electronic device.

In another embodiment, an electronic chip package is provided. The package includes a base defining a fluid inlet opening for receiving pressurized fluid from a fluid source and a fluid outlet opening. A dielectric body is arranged on the base and configured to support an electronic device. The dielectric body comprises a coolant flow chamber formed in a first surface thereof, and a plurality of impingement openings formed through the body within the coolant flow chamber. The plurality of impingement openings are in communication with the fluid inlet opening of the base for generating a plurality of fluid streams to be expelled into the coolant flow chamber. The body further comprises a coolant return port formed within the coolant flow chamber and in communication with the fluid outlet opening of the base.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross section view of a conventional remote cooling system.

FIG. 2 is a simplified cross section view of an embedded cooling system utilizing jet impingement cooling according to an embodiment of the present disclosure.

FIG. 3A is a simplified exploded perspective view of a jet impingement cooled chip package according to an embodiment of the present disclosure.

FIG. 3B is an assembled perspective view of the jet impingement cooled chip package according to the embodiment of FIG. 3A.

FIG. 4A is a perspective view of a jet impingement cooled chip package according to another embodiment of the present disclosure.

FIG. 4B is a partial section view of the jet impingement cooled chip package of FIG. 4A.

DETAILED DESCRIPTION

It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, many other elements found in electronic circuits and associated cooling systems, including embedded cooling systems configured for cooling integrated circuits. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. The disclosure herein is directed to all such variations and modifications known to those skilled in the art.

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. Furthermore, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout several views.

Embodiments of the present disclosure include the integration of micro-fluidic jet impingement cooling into an electronics package (e.g. a dielectric substrate of an MMIC device) for directly cooling targeted electronic devices or other heat-generating active components housed on or within the package. In one embodiment, a package substrate or body formed of a dielectric material (e.g. ceramic) includes a plurality of impingement jets or openings defining outlet nozzles formed therein. The impingement openings are configured (e.g. sized and located) for communication with a source of pressurized fluid or coolant. One or more coolant flow chambers and one or more coolant return channels may also be formed through all or a portion of the package body. The package body is configured to support one or more electronic devices or chips which may be hermetically attached to a surface thereof, and positioned over the plurality of impingement openings such that fluid expelled therefrom contacts a surface of the one or more devices for providing a direct cooling function.

Embodiments set forth herein may be implemented in a co-fired ceramic substrate, for example, a low temperature co-fired ceramic (LTCC) and/or a high temperature co-fired ceramic (HTCC) brazed to a metal base plate. Ceramic is particularly well-suited for direct attachment of the electronic device or chip due to its coefficient of thermal expansion which closely matches typical chip materials. Wire or ribbon bonds may be used to electrically interconnect the chip to portions of the package.

Embodiments of the present disclosure further include methods of manufacturing chip packages according to the above-described embodiments. An exemplary chip package may be manufactured by mechanically forming (e.g. punching) or laser drilling holes and/or cavities in individual layers of a dielectric substrate material (e.g. ceramic) while in their “green” or pre-fired state. In one embodiment, inlet and/or outlet coolant channels may be formed in one or more first or lower substrate layers. A plurality of impingement openings may be formed in one or more second or intermediate substrate layers. An opening defining a coolant flow chamber may be formed in one or more third or upper substrate layers. The inlet and outlet coolant channels, the plurality of impingement openings, and the opening defining the coolant flow chamber are positioned such that when the first, second and third substrate layers are aligned (e.g. stacked) on top of one another and laminated to form a completed package, pressurized fluid may be communicated to the plurality of impingement openings via the inlet coolant channel for generating a plurality of fluid streams expelled into the coolant flow chamber. In a particularly advantageous embodiment, the impingement openings may be positioned directly below an electronic device (and more particularly, a heat-generating source thereof) configured to be mounted to an upper surface of the third substrate layer(s). In this way, fluid expelled from the plurality of impingement openings directly contacts an underside of the electronic device, maximizing heat transfer therefrom.

Referring generally to FIG. 2, a simplified exemplary embedded cooling system 20 according to an embodiment of the present disclosure is shown. As illustrated, in contrast to the conventional remote cooling system 10 illustrated in FIG. 1, an embedded cooling arrangement delivers pressurized coolant 23 into close proximity with a circuit die 21 via fluid passages 22 formed through a package body on which circuit die 21 is supported. More specifically, coolant 23 from the “system level” heat sink or cold plate 29, is brought (e.g. pumped) through an intermediate fluid routing means embodied as a multi-layer ceramic package 25. Ceramic package 25 is configured to receive pressurized fluid and generate a plurality of fluid streams for contacting with a base or bottom side of circuit die 21 supported thereon. An epoxy layer 26 may be provided for attaching ceramic package 25 to cold plate 29.

In the illustrated embodiment, coolant 23 is conveyed via centrally located internal passages 22 formed through ceramic package 25, and directly contacts an underside of circuit die 21. In other embodiments, coolant 23 may not directly contact circuit die 21, but rather, may be contained in a self-sealed chamber defined in ceramic package 25 to which circuit die 21 is mounted. In this embodiment, a thin layer of material, such as solder or epoxy, may be used to join circuit die 21 to ceramic package 25. In these embodiments, however, the presence of the intermediate joining material may degrade performance to some degree, depending upon the thickness and thermal conductivity of the joining material used.

An advantage of embedded cooling systems according to embodiments of the present disclosure, such as those set forth above with respect to FIG. 2, is the elimination of a number of thermal interfaces between a cooling fluid or coolant and a heat source. In practice, such elimination can translate into a reduction in the overall thermal resistance from junction to coolant. The reduced thermal resistance, in turn, results in lower operating temperatures for a given circuit die dissipation, or conversely, allows a larger heat dissipation for a given temperature rise.

Referring generally to FIGS. 3A and 3B, simplified exploded (FIG. 3A) and assembled (FIG. 3B) illustrations of a micro jet impingement cooled package 50 according to an embodiment of the present disclosure are shown. Package 50 includes a circuit element or die 80 (e.g. a GaN/SiC integrated circuit such as one or more amplifiers). Circuit die 80 includes heat generating elements, such as FETs 81. Circuit die 80 is configured to be mounted to and supported by a substrate body 60 formed from a plurality of substrate layers 62,63,64,65,66. Each substrate layer 62,63,64,65,66 may comprise a dielectric material, for example, a section of ceramic tape having a thickness of approximately 2 mils.

In an assembled state, circuit die 80 may be arranged within an aperture 61 formed (e.g. mechanically punched or machined) in first substrate layer 62. First substrate layer 62 includes electrical circuits and/or pathways 67 formed thereon (e.g. printed thereon in the pre-fired state of the substrate layer) for generating required electrical connections to circuit die 80. Circuit die 80 may be connected to these features via conventional wire and/or ribbon bonding processes as illustrated.

Second substrate layer 63 is arranged vertically below or beneath first substrate layer 62 and defines a hermetic circuit die mounting surface 71 on a first or top surface thereof. Circuit die 80 may be supported by and hermetically sealed about its lower perimeter surface to surface 71 of second substrate layer 63 using either a solder or epoxy attachment material to form a leak-tight seal. Second substrate layer 63 further includes an aperture or opening 83 formed therethrough. Opening 83 may be sized and positioned such that a targeted area, such as an area associated with FETs 81 of circuit die 80, is arranged over opening 83 in an assembled state of the package. Opening 83 is used to form a recessed area in the substrate body. More specifically, joining first substrate layer 62, second substrate layer 63, and a third substrate layer 64 creates a recessed area or coolant flow chamber 82 centrally positioned and defined between a top surface of third substrate layer 64 and a bottom surface of circuit die 80.

Substrate body 60 includes an integrated fluid manifold formed therein for generating a series of high velocity fluid streams or “impingement jets” from a received pressurized fluid (coolant). These impingement jets are formed via a plurality of impingement openings or impingement nozzles 92 formed through a portion of substrate body 60. More specifically, in the exemplary embodiment, substrate layers 64,65,66 each include a plurality of apertures 92′ formed therethrough (e.g. laser or mechanically drilled) such that when substrate layers 64,65,66 are assembled together (e.g. laminated), apertures 92′ align (i.e. are coaxial), forming three-dimensional impingement openings 92 through substrate body 60. One or more fluid return ports is also defined through substrate body 60 via respective apertures or openings 84 formed through each substrate layer 64,65,66. As shown, impingement openings 92 are positioned such that when circuit die 80 is arranged on second substrate layer 63, impingement openings 92 are arranged proximate (i.e. under) a bottom surface of circuit die 80.

Substrate body 60 may be supported by a base 75 (e.g. a metal base). Base 75 includes an inlet opening or inlet port 76 configured for communication with a pressurized fluid source (not shown), for example, a liquid cooled cold plate. As illustrated, in an assembled state, inlet opening 76 will correspond in location to impingement openings 92 such that impingement openings 92 are arranged in fluid communication with inlet opening 76. A return opening or return port 77 is also defined through base 75 and configured for fluid communication with a fluid return portion of the pressurized fluid source. Return opening 77 corresponds in location to the return portion defined by openings 84 for receiving fluid therefrom.

Still referring to FIGS. 3A and 3B, a raised peripheral protrusion or sealing ring 78 surrounding circuit die 80 may be formed on a top surface of first substrate layer 62. Sealing ring 78 may be formed from, for example, a plurality of stacked ceramic substrate layers, each having a like-sized opening 79 formed therein. A lid (not shown) may be placed on sealing ring 78 during the manufacturing process of package 50 for hermetically sealing circuit die 80 within substrate body 60. The lid may be soldered to the package ceramic or attached by welding to sealing ring 78, which may be brazed to the package during the co-firing process. This hermetically sealed lid forms a protective barrier between the coolant and the rest of the system in the event of a catastrophic failure of the chip.

In operation, and referring to FIG. 3A, pressurized fluid or coolant (illustrated via vertical arrows) provided by an external source is communicated to impingement openings 92 via inlet opening 76 of base 75. Depending on a target flow rate, fluid supplied to inlet opening 76 may be pressurized to approximately 30 to 100 pounds per square inch (PSI). Pressurized fluid streams are expelled from the ends of each impingement opening 92 for contacting an underside of circuit die 80. After impinging on circuit die 80, expelled fluid is collected in coolant flow chamber 82 and exits package 50 via fluid return openings 84 defined through substrate body 60, as well as return opening 77 formed through base 75. By way of non-limiting example, an exemplary fluid or coolant useful in embodiments of the present disclosure comprises a mixture of 40% propylene glycol and 60% water. While embodiments of the present disclosure have been described as implementing liquid cooling, it should be understood that other embodiments may utilize gas (e.g. air) cooling implemented within a similar substrate structure.

The circuit package illustrated in FIGS. 3A and 3B illustrates an exemplary, simplified embodiment of the present disclosure. It should be understood, however, that many variations may exist without departing from the scope of the present disclosure. For example, any number of substrate layers may be used to construct a substrate body of any desired size and configuration. Likewise, the position, size and any other characteristic of, for example, the impingement openings and the inlet and return openings, can be modified according to a particular application.

While embodiments of a chip package disclosed herein have been described as constructed from a layering process, it should be understood that other fabrication techniques may be used without departing from the scope of the present disclosure. For example, three-dimensional printing processes may be implemented to form the substrate bodies described therein as monolithic or singular structures. It should be understood that by utilizing these alternative processes, the configuration of, for example, the impingement openings, as well as other fluid routing means may be altered to include, by way of non-limiting example only, fluid channels or pathways that not only move fluid vertically within a substrate body, but also horizontally and/or diagonally. These processing methods also allow for the formation of additional features on or within the coolant flow chambers described above. For example, a plurality of protrusions may be formed on a surface of the coolant flow chamber and positioned for diverting coolant flow around impingement openings so as to ensure their ability function in an unaffected manner.

Further still, while not illustrated for the purpose of simplicity, embodiments of the preset disclosure may include additional electrical circuits and/or pathways printed on one or more of the substrate layers in their green state beyond those illustrated on first substrate layer 62 as shown and described with respect to FIGS. 3A and 3B. Likewise, vias or other conductive features for connecting these or other circuits through the substrate layers may be created (e.g. drilled and filled with conductor paste) while the substrate layers are in a pre-fired state. Thus, in addition to integrated cooling provisions, embodiments of the present disclosure may also integrate power distribution, digital control, RF transmission lines and other the electrical circuit components into and/or through the package. In this way, embodiments of the present disclosure include packages containing all required electrical circuits in addition to the coolant inlet channels, impingement openings, coolant flow chambers, hermetic chip mounting surfaces and coolant return channels needed to achieve jet impingement cooling of one or more electrical devices housed within the package.

As set forth above, direct impingement cooling on an underside of a heat generating circuit element or chip has the benefits of eliminating materials (i.e. thermal junctions) between the chip and coolant, providing enhanced heat transfer therebetween. It should be understood, however, that for jet impingement cooling to perform most efficiently, a suitable ratio between a diameter (d) of the impingement openings or nozzles, and a distance (h) between these openings and a heated surface (e.g. an underside of a chip or circuit die) is required. The h/d ratio is also a function of velocity (v) of the fluid expelled from the impingement opening. In one embodiment, finite element thermal analysis may be performed to determine optimized d, h, and v values for the particular heat flux geometry of the chip or circuit being cooled.

It should be understood that fluid velocity can be changed by manipulating the coolant inlet pressure for a fixed nozzle diameter, while the h/d ratio can be established during the manufacture of dielectric or ceramic tape layer structure (i.e. the substrate body). Specifically, nozzle diameter is predetermined and fixed when the impingement openings are formed through each substrate layer. The nozzle-to-heated surface distance is set, in the above-illustrated embodiments, according to the number of substrate layers and their respective thickness used to form the coolant flow chamber under the circuit die. Other features, such as tapered impingement openings for further manipulating the shape of the fluid streams (i.e. converging or diverging) expelled therefrom are also envisioned. Tapered impingement openings may be formed by, for example, altering the size of the apertures formed through successive substrate layers, or by forming each aperture with its own taper.

Embodiments of the present disclosure have been described as providing direct contact between generated fluid streams and a surface of a circuit die to be cooled. However, other advantageous embodiments are envisioned which provide nearly the same thermal benefits as these embodiments, while facilitating easier repair in the event of a failed circuit die. In these alternate embodiments, a highly temperature-conductive shim is placed into the package where the circuit die had previously been described as being arranged. The shim can be attached to the substrate body using a high temperature braze or solder alloy. The heat producing circuit die is then attached to the shim using a high conductivity epoxy or solder which is cured or re-flowed at a temperature lower than the braze alloy used to hermetically attach the shim. The back side of the shim is then cooled using jet impingement as previously described. The heat producing chip can then be removed and replaced if it is found to be defective without damaging the package or compromising the integrity of the hermetic coolant joint in the package.

FIG. 4A illustrates a removable module 100 according to an embodiment of the present disclosure. Module 100 includes an electronic chip package 105 supported on an associated base or cold plate 110. Chip package 105 may comprise a similar multi-layer dielectric (e.g. ceramic) structure as shown and described with respect to FIGS. 3A and 3B. In the illustrated embodiment, however, chip package 105 comprises a plurality of circuit chips or circuit dies 112 housed thereby.

Cold plate 110 includes integrated coolant inlet and outlet ports 116,118 for delivering pressurized fluid to and from package 105 via internal fluid channels (not shown). Ports 116,118 are further configured to transport fluid to and from a host cooling system (e.g. a larger cold plate, not shown). In this way, a cold plate 110 serves as an fluid-transporting interface between chip package 105 and an external environment.

As illustrated, surrounding a portion of the plurality of circuit elements 112 are raised peripheral protruding surfaces or sealing rings 126. As set forth above with respect to FIGS. 3A and 3B, a corresponding lid (not shown) may be placed on each sealing ring 126 for hermetically sealing each circuit element within package 105. The lids may be soldered to the package ceramic or by welding to sealing rings 126. Sealing rings 126 may be brazed to the package during the co-firing process. The hermetically sealed lid forms a protective barrier between the coolant and the rest of the system in the event of a catastrophic failure of the chip. As a respective one of a plurality of sealing rings 126 and lids may be used to cover, for example, each circuit die 112 individually, this arrangement may prevent the failure of a single circuit die from damaging the remainder of the circuit dies in a package or adjacent assembly.

FIG. 4B is a perspective view of a section of the system of FIG. 4A shown with one circuit die 112 removed from chip package 105 for clarity. Similar to the embodiments of FIGS. 3A and 3B, package 105 includes a coolant flow chamber 120 defined therein. Impingement openings or nozzles 122 are also formed through package 105 (e.g. through ceramic substrate layers thereof) and placed in fluid communication with pressurized fluid from inlet port 116 of cold plate 110 for generating pressurized fluid streams. Impingement openings 122 are positioned such that these fluid streams contact circuit element 112 in advantageous locations, such as directly underneath its heat-generating elements (e.g. FETs). Likewise, outlet or return openings 124 are formed through package 105 (e.g. through ceramic substrate layers thereof) and are in fluid communication with output port 118 of cold plate 110 for carrying heated fluid out of coolant flow chamber 120 after impinging on circuit element 112.

Embodiments and applications of the present disclosure include, but are not limited to, applications to cool Transmit/Receive (T/R) module components. In radar applications this implementation could be represented by n×m number of transmit/receive (T/R) modules in a phased array antenna. Embodiments may also be implemented to improve thermal management of high power amplifier (HPA) assemblies, GaN/SiC, GaN/Diamond and other MMIC semiconductor material devices, laser diode packages, and the like. Embodiments provide particular advantages for cooling non-dilated millimeter wave actively electronically scanned arrays (AESAs), wherein the tight spacing (approximately 0.100″) between elements prevents sufficient cooling using traditional means to avoid significant performance degradation. Embodiments of the present invention yield significant benefits with regards to efficiency, power out, and lifespan associated with such devices and/or assemblies.

While the foregoing invention has been described with reference to the above-described embodiment, various additional modifications and changes can be made without departing from the spirit of the invention. Accordingly, all such modifications and changes are considered to be within the scope of the appended claims. Accordingly, the specification and the drawings are to be regarded in an illustrative rather than a restrictive sense. The accompanying drawings that form a part hereof, show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations of variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. 

What is claimed is:
 1. A substrate body for supporting an electronic device, comprising: at least one electrical circuit formed on or within the body and configured to be connected to the electronic device; and a plurality of impingement openings formed through the body, each impingement opening responsive to a source of pressurized fluid for generating a fluid stream expelled in a direction of the electronic device.
 2. The substrate body of claim 1, wherein the body comprises a plurality of laminated layers of dielectric material.
 3. The substrate body of claim 2, wherein the plurality of laminated layers comprise layers of ceramic material.
 4. The substrate body of claim 1, further comprising a recessed area formed in a first surface of the body, wherein the plurality of impingement openings are defined within said recessed area.
 5. The substrate body of claim 4, further comprising at least one fluid return opening formed through the body and in communication with the recessed area.
 6. The substrate body of claim 1, wherein the plurality of impingement openings are oriented such that the plurality of fluid streams expelled thereby are configured to directly impinge on a surface of the circuit device supported by the body.
 7. The substrate body of claim 4, wherein the recessed area is vertically aligned relative to the electronic device.
 8. The substrate body of claim 2, wherein the plurality of laminated layers of dielectric material are arranged in stacked relation to one another.
 9. An electronic chip package comprising: a base including a fluid inlet opening for receiving pressurized fluid from a fluid source and a fluid outlet opening; and a dielectric body arranged on the base and configured to support an electronic device, the body including: a coolant flow chamber formed in a first surface thereof; a plurality of impingement openings formed through the body within the coolant flow chamber, the plurality of impingement openings in communication with the fluid inlet opening of the base for generating a plurality of fluid streams to be expelled into the coolant flow chamber; and a coolant return port formed through the body within the coolant flow chamber and in communication with the fluid outlet opening of the base, wherein the plurality of impingement openings are positioned such that a plurality of fluid streams to be generated are configured to directly impinge on the surface of the electronic device mounted to the first surface of the body.
 10. The package of claim 9, wherein the base comprises a thickness and the fluid inlet opening and fluid outlet opening are formed through the base in a direction of the thickness.
 11. The package of claim 10, wherein the dielectric body further comprises: a first dielectric layer having a first thickness and including an aperture formed therethrough in a direction of the first thickness for defining the coolant flow chamber; and a second dielectric layer having a second thickness, wherein the plurality of impingement openings and the coolant return port are formed through the second dielectric layer in a direction of the second thickness.
 12. The package of claim 9, wherein the fluid inlet opening, the plurality of impingement openings, and the coolant flow chamber are oriented such that fluid from the fluid source may uninterruptedly pass through the fluid inlet opening, the plurality of impingement openings, and the coolant flow chamber in a first direction.
 13. An electronic chip package comprising: a base including a fluid inlet opening for receiving pressurized fluid from a fluid source and a fluid outlet opening; and a dielectric body having a first side arranged on the base, and a second side opposite the first side configured to support an electronic device arranged thereon, the body including: a coolant flow chamber formed in the second side of the body, the coolant flow chamber configured to be in fluid communication with an exposed surface of the electronic device when the electronic device is supported by the body; a plurality of impingement openings formed through the body within the coolant flow chamber, the plurality of impingement openings in communication with the fluid inlet opening of the base for generating a plurality of fluid streams to be expelled into the coolant flow chamber; and a coolant return port formed through the body within the coolant flow chamber and in communication with the fluid outlet opening of the base.
 14. The package of claim 13, wherein the fluid inlet opening, the plurality of impingement openings, and the coolant flow chamber are oriented such that fluid from the fluid source may uninterruptedly pass through the fluid inlet opening, the plurality of impingement openings, and the coolant flow chamber in a first direction.
 15. The package of claim 14, wherein the dielectric body further comprises: a first layer of dielectric material having a first thickness and including an aperture formed therethrough in a direction of the first thickness for defining the coolant flow chamber; and a second layer of dielectric material having a second thickness, wherein the plurality of impingement openings and the coolant return port are formed through the second dielectric layer in a direction of the second thickness, wherein the base comprises a third thickness and the fluid inlet opening and fluid outlet opening are formed through the base in a direction of the third thickness, and wherein the first direction comprises the direction of the first, second, and third thicknesses.
 16. The package of claim 15, wherein the first and second layers of dielectric material comprise a ceramic material.
 17. The package of claim 15, wherein a recessed area is formed in a top surface of the layer of dielectric material proximal to the electronic device and in vertical alignment therewith, and wherein the plurality of impingement openings are defined within said recessed area. 